Refereed Conferences - Abstracts Only

  1.  “Design of Reconfigurable Threshold Logic Using DG-MOSFETs“, S Kaya and F A Hamed, 12th Int. Workshop of Computational Electronics – IWCE’12, 08-10 October, 2007, Amherst, MA, USA
  2. “Ion Permeation and Binding in Biomolecular Ion Pumps via Molecular Dynamics “, J E Fonseca, R F Rakowski, and S Kaya, 12th Int. Workshop of Computational Electronics – IWCE’12, 08-10 October, 2007, Amherst, MA, USA
  3. “Low-power tunable nanocircuits with DG-MOSFETs for current sensing applications, S Kaya and H F A Hamed, SPIE Photonics East – Session 6769: Nanosensing: Materials, Devices, and Systems III., 9-12 September 2007, Boston, MA, USA
  4. “Reconfigurable Threshold Logic Gates with nano-scale DG-MOSFETs”, S Kaya, and H F A Hamed, Nano Giga Challenges in Electronics and Photonics, 12-14 March 2007, Phoenix, AZ, USA
  5. “Compact Tunable Current-Mode Analog Circuits Using DG-MOSFETs”, H Hamed, S Kaya, and J Starzyk, 2006 IEEE Int. SOI Conference, 2-5 October, 2006, Niagara Falls, NY, USA.
  6. “Modeling of Binding Sites and Electrostatics in the Ion-Motive Sodium Pump”, J F Fonseca, S Kaya, R F Rakowski and S Guennoun, 6th IEEE Conference on Nanotechnology – IEEENano 2006, 16-20 July, 2006, Cincinnati, OH, USA
  7. “Low-Power Tuneable Analog Circuit Blocks Based on Nanoscale Dual-Gate MOSFETs”, S Kaya, H Hamed and J Starzyk, 6th IEEE Conference on Nanotechnology – IEEENano 2006, 16-20 July, 2006, Cincinnati, OH, USA
  8. “Power•Delay Product in COSMOS Logic Circuits”, A Al-Ahmadi and S Kaya, 11th Int. Workshop of Computational Electronics – IWCE’11, 25-27 May, 2006, Vienna, Austria.
  9. “Electrostatic Modeling of Ion Motive Sodium Pump”, J F Fonseca, S Kaya, and R F Rakowski, 11th Int. Workshop of Computational Electronics – IWCE’11, 25-27 May, 2006, Vienna, Austria.
  10.  “Prediction of the location of binding sites in homology models of metal and alkaline-earth ion binding proteins”, Reddy C , J F Fonseca, S Guennoun, S Kaya and R F Rakowski., Swiss Biomedical Research Meeting - USGEB , 23-24 Feb 2006, Geneva, Switzerland. 
  11. “Layout and Geometry Tolerances in COSMOS”, A Al-Ahmadi and S Kaya, International Semiconductor Device Research Symposium – ISDRS, 6-9 Dec 2005, Washington DC, USA.
  12. “Study of Dual-Gate SOI MOSFETs as RF Mixers”, Swetha Varadharajan and S Kaya, International Semiconductor Device Research Symposium – ISDRS, 6-9 Dec 2005, Washington DC, USA.
  13. “Homology Study of Na,K ATPases Based on SERCA “, J F Fonseca, S Kaya and R F Rakowski, Mechanisms Of Membrane Transport – A Gordon Research Conference, 5-10 June, 2005, Tilton, New Hampshire, USA.
  14. “Device Scaling in COSMOS Architecture”, A Al-Ahmadi and S Kaya, IEEE 63rd Device Research Conference – DRC’63, 20-22 June, 2005, Santa Barbara, California, USA
  15. “Electro-Chemical Modeling Challenges of Biological Ion Pumps”, R F Rakowski, S Kaya and J F Fonseca, 10th Int. Workshop of Computational Electronics – IWCE’10, 24-26 Oct, 2004, West Lafayette, Indiana, USA.
  16. “Search for Optimum and Scalable COSMOS”, S Kaya and A Al-Ahmadi, 10th Int. Workshop of Computational Electronics – IWCE’10, 24-26 Oct, 2004, West Lafayette, Indiana, USA.
  17. “RF Performance of Strained SiGe pMOSFETs: Linearity and Gain”, W Ma and S Kaya, 10th Int. Workshop of Computational Electronics – IWCE’10, 24-26 Oct, 2004, West Lafayette, Indiana, USA.
  18. “Simulation of Interface Roughness in DGMOSFETs using Non-Equilibrium Greens Functions”, J Fonseca and S Kaya, IEEE 62nd Device Research Conference – DRC’62, 21-23 June, 2004, South Bend, Indiana, USA
  19. “COSMOS: A New MOS Device Device Paradigm”, S Kaya, Silicon Nanoelectronics Workshop – VLSI Symposia,13-14 Jun 2004, Honolulu, Hawaii,USA.
  20. “Simulation of Interface Roughness in DG-MOSFETs using Non-Equilibrium Green’s Functions”, J Fonseca and S Kaya, IEEE 34th SISC, 04-06 Dec, 2003, Washington, DC.
  21.  “Impact of Device Physics on DG and SOI MOSFET Linearity“, W Ma and S.Kaya, Int. Semiconductor Device Research Symposium -ISDRS, 10-12 Dec, 2003, Washington, DC.
  22. J Fonseca and S.Kaya, “Accurate Treatment of Interface Roughness in Nanoscale DGMOSFETs using Non-Equilibrium Green’s Functions”, Int. Semiconductor Device Research Symposium - ISDRS, 10-12 Dec, 2003, Washington, DC
  23. “Design of DG-MOSFETs for High Linearity Performance”, S.Kaya, W Ma and A.Asenov, ,IEEE Int. SOI  Conference, Sep 2003, Newport Beach, California, USA.
  24. “Electro-thermal Analysis of RF Linearity in DG and SOI MOSFETs”, W Ma and  S.Kaya, 4th OSC Graduate Student Workshop and Conference, 07-08 Aug 2003, Ohio Supercomputer Center, Columbus, Ohio, USA.
  25. “Accurate Treatment of Interface Roughness in Nanoscale MOSFETs using Non-Equilibrium Green’s Functions”, J Fonseca and  S.Kaya, 4th OSC Graduate Student Workshop and Conference, 07-08 Aug 2003, Ohio Supercomputer Center, Columbus, Ohio, USA.
  26. “Study of RF Linearity in sub-50nm MOSFETs Using Simulations”, W Ma, S.Kaya and A.Asenov, , 9th Int. Workshop of Computational Electronics – IWCE’9, 26-29 May 2003, Frascati, Rome, Italy.
  27. “Breakdown of Universal Mobility due to Atomistic Interface Considerations in nano-MOSFETs”, S Kaya and A Asenov, 4th Motorola Workshop on Computational Materials and Electronics, 14-15 Nov 2002, Tempe, AZ, USA.
  28. “Breakdown of Universal Mobility Curves in sub-100nm MOSFETs”, S Kaya, A Asenov and S. Roy, Silicon Nanoelectronics Workshop – VLSI Symposia,9-10 Jun 2002, Honolulu, HI,USA.
  29. “Implications of Imperfect Interfaces and Edges in Ultra-small MOSFET Characteristics”, A Asenov, S Kaya and A R Brown, 3rd Motorola Workshop on Computational Materials and Electronics, 12-14 Nov 2001, Tempe, AZ, USA.
  30. “On the breakdown of Universal Mobility Curves: A 3D Statistical Simulation Framework”, S Kaya, A Asenov and S. Roy, 8th Int. Workshop of Computational Electronics – IWCE’8, Oct 2001, Urbana-Champaign, IL,USA.
  31. 3D Modelling of Imperfect Interfaces and Edges in MOSFETs, S Kaya, A Brown, S. Roy and A Asenov,  Quantum Transport Workshop, 17-22 June 2001, Maratea, Italy.
  32. “Statistical 3D Simulation of Line Edge roughness in Decanano MOSFETs”, A Brown, S Kaya, A Asenov, J H Davies and T. Linton, Silicon Nanoelectronics Workshop – VLSI Symposia,10-11 Jun 2001, Kyoto, Japan.
  33. “Drift Diffusion and Hydrodynamic Simulations of Si/SiGe p-MOSFETs”, Y P Zhao, J R Watling, S Kaya, A Asenov and J R Barker, 5th IUMRS Int. Conference on Advanced Materials, 13-18 Jun 1999, Beijing, China.
  34. “Monte Carlo Investigation of Optimal Device Architectures for SiGe FETs”, S Roy, S Kaya, S Babiker, A Asenov and J R Barker, 6th Int. Workshop of Computational Electronics – IWCE 6, Oct 1998, Osaka, Japan.
  35. “Velocity Overshoot in psuedomorphic Si0.8Ge0.2p-MOSFET’s”, G Ansaripour, G Braithwaite, E H C Parker and T E Whall, S Kaya, Y-P Zhao, J R Watling, A Asenov, J R Barker, 8th European Heterostructure Technology Workshop, 13-15 Sep 1998, Cardiff, UK.
  36. “Strained Si/SiGe Quantum Wells and Wires on Vicinal (118) Si Substrates”, S Kaya, T J Thornton, K Fobelets, P W Green and J M Fernandez, Silicon Nanoelectronics Workshop – VLSI Symposia, 8-9 Jun 1997, Kyoto, Japan. 

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