Conferences

FULL PAPERS IN CONFERENCE PROCEEDINGS

  1. iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture,” D DiTomaso, A Kodi, S Kaya, D Matolak, IEEE 19th Annual Symposium on High Performance Interconnects – HOTI, pp.11-18, 24-26 Aug. 2011, Santa Clara, USA.
  2. On Tunable Compact Analog Circuits with Nanoscale DG-MOSFETs“, S Kaya and H F A Hamed, Proc. Int. 53rd Midwest Symposium on Circuits and Systems – MWSCAS’53 1-4 August 2010, Seattle, WA, USA.
  3. Studies of Ni and Co doped amorphous AlN for magneto-optical applications”, W. M. Jadwisienczak, H. Tanaka, M. Kordesch, A. Khan, S. Kaya, R. V. Vuppuluri, MRS Fall 2009, Nov 30-Dec 4, Boston, MA, USA
  4. “A Novel Voltage-Controlled Ring Oscillator Based on Nanoscale DG-MOSFETs”, S Kaya & A Kulkarni, 20th IEEE Int. Conf. on Microelectronics – ICM’08, 14-17 December 2008, Dubai, UAE.
  5. “Low-Voltage Tunable Double-Gate MOSFET Transconductor for VHF/UHF Continuous-Time Filters”, H F A Hamed and S Kaya, 19th IEEE Int. Conf. on Microelectronics – ICM’07 29-31 December 2007, Cairo Egypt.
  6. “Low-power tunable nanocircuits with DG-MOSFETs for current sensing applications, S Kaya and H F A Hamed, SPIE Prooceedings 6769 – Nanosensing: Materials, Devices, and Systems III, 9-12 September 2007, Boston, MA, USA
  7. “Low Voltage Programmable Double-Gate MOSFETs Current Mirror and its As Programmable-Gain Current Amplifier”, H F A Hamed, S Kaya, 14th IEEE Int. Conference on Electronics, Circuits and Systems – ICECS’07, 11-14 December, 2007, Marrakech, Morocco.
  8. “Models, Electrostatics and Molecular Dynamics of the Na+/K+-ATPase”, J F Fonseca, R F Rakowski and S Kaya, Ohio Collaborative Conference on Bioinformatics – OCCBIO 2006, 28-30 Jun 2006, Athens, OH, USA. http://www.occbio.org
  9. “A Novel Single-Gated Strained CMOS Architecture: COSMOS”, A Al-Ahmadi and S Kaya, Int. Conference on Simulation of Semiconductor Process and Devices – SISPAD, 1-3 Sep 2005, Tokyo, Japan.
  10. “Study of RF Performance for Graded-Channel SOI MOSFETs”, W Ma and S Kaya, Int. Conference on Simulation of Semiconductor Process and Devices – SISPAD, 1-2 Sep 2005, Tokyo, Japan.
  11. “Scaling of RF Linearity in DG and SOI MOSFETs”, W Ma, S Kaya, and A Asenov, 11th IEEE Int. Symposium on Electron Devices for Microwave and Optoelectronic Applications – EDMO, 17-18 Nov 2003, Orlando, FL, USA.
  12. “Enhanced Velocity Overshoot and Transconductance in Si/Si0.64Ge0.36/Si p-MOSFETs – Predictions for Deep Submicron Devices”, M Palmer, G Braithwaite, M J prest, T E Whall, E H C Parker, Y P Zhao, S Kaya, J R Watling, A Asenov, J R Barker,A Waite and A G R Evans , Proc. of 31st European Solid-state Device Research Conference – ESSDERC, 11-13 Sep 2001, Nunberg, Germany.
  13. “Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1mm MOSFETs”, S Kaya, A R Brown, A Asenov, D Magot and T Linton, Int. Conference on Simulation of Semiconductor Process and Devices – SISPAD, 5-8 Sep 2001, Athens, Greece.
  14. “Single stage amplifiers on a CMOS grade silicon substrate using a polymer interlayer dielectric with strained silicon MOSFETs” G Ternent, D L Edgar, E H McLelland, F Williamson, N Ferguson, S Kaya, C D W Wilkinson, I G Thayne, K Fobelets, J Hampson, Asia-Pacific Microwave Conference, p.767, 3-6 Dec 2000, Sydney, Australia.
  15. “Indication of Non-equilibrium Transport in SiGe p-MOSFETs” Y P Zhao, S Kaya, J R Watling, A Asenov, J R Barker, M Palmer, G Braithwaite, T E Whall, E H C Parker, A Waite and A G R Evans, Proc. of 30th European Solid-state Device Research Conference – ESSDERC, p.224, 11-13 Sep 2000, Cork, Ireland.
  16. “Metal Gate Strained Silicon SiGe MOSFETs for Microwave Integrated Circuits”, G Ternent, D L Edgar, H McLelland, S Ferguson, S Kaya, C D W Wilkinson and I G Thayne 8th IEEE Int. Symposium on Electron Devices for Microwave and Optoelectronic Applications – EDMO, 13-14 Nov 2000, Glasgow, Scotland.
  17. “Effect of Oxide Interface Roughness on the Threshold Voltage Fluctuations in Decanano MOSFETs with Ultrathin Gate Oxides” A Asenov and S Kaya, Int. Conference on Simulation of Semiconductor Process and Devices – SISPAD, 5-8 Sep 2000, Seattle, USA.
  18. “RF Analysis Methodology for Si and SiGe FETs Based on Transient Monte Carlo Simulation”, S Roy, S Kaya, A Asenov and J R Barker, Int. Conference on Simulation of Semiconductor Process and Devices – SISPAD, 6-8 Sep 1999, Kyoto, Japan.
SHORT ABSTRACTS:
  1. “Use Of Nanomechanics Techniques To Evaluate The Moisture Damage Phenomenon In Warm Mix Asphalt”, M. Nazzal, S. Kaya, L. Abu-Qtaish, The 2nd International Symposium On Asphalt Pavements & Environment, Fortaleza, Brazil, 2011
  2. “Ultra-Compact Low-Power ICO/VCO Circuits with Double Gate MOSFETs”, S. Laha, K.C. Wijesundara, A. Kulkarni, S. KayaIEEE International Semiconductor Device Research Symposium – ISDRS, 7-9 Dec 2011, Washington DC, USA.
  3. “Temporal and Steric Analysis Of Ionic Permeation and Binding in Na+,K+-ATPase via Molecular Dynamic Simulations”, J. E. Fonseca and S. KayaBiophysical Journal, vol.96, Issue 3, 145a. Abstract submitted to the Biophysical Society Meeting, 28 Feb-4Mar, 2009, Boston, MA, USA.
  4. “Highly Reconfigurable and Error Tolerant Threshold Logic Gates Based on Nanoscale DG-MOSFETs”, S Kaya, D T-Y Ting and H F A Hamed, International Semiconductor Device Research Symposium – ISDRS, 9-11 Dec 2009, Washington DC, USA.
  5. “Study of Ion-Motive ATPase Proteins for Multi-Valued Logic and Storage “J E Fonseca, K Clark, S-W Hla, R F Rakowski and S KayaNSF EMT Workshop, 24-25 July, 2008, Princeton, NJ, USA
  6. “Nanocircuits for Sensors and On-Chip Analog Signal Processing“, A Kulkarni and S KayaInt. Conf. on Nanoscale Spectroscopy & Nanotechnology 5 – NSS5, 15-19 Jul7, 2008, Athens, OH, USA
  7. “Design of Reconfigurable Threshold Logic Using DG-MOSFETs“, S Kaya and F A Hamed, 12th Int. Workshop of Computational Electronics – IWCE’12, 08-10 October, 2007, Amherst, MA, USA
  8. “Ion Permeation and Binding in Biomolecular Ion Pumps via Molecular Dynamics “, J E Fonseca, R F Rakowski, and S Kaya12th Int. Workshop of Computational Electronics – IWCE’12, 08-10 October, 2007, Amherst, MA, USA
  9. “Reconfigurable Threshold Logic Gates with nano-scale DG-MOSFETs”, S Kaya, and H F A Hamed,Nano Giga Challenges in Electronics and Photonics, 12-14 March 2007, Phoenix, AZ, USA
  10. “Compact Tunable Current-Mode Analog Circuits Using DG-MOSFETs”, H Hamed, S Kaya, and J Starzyk, 2006 IEEE Int. SOI Conference, 2-5 October, 2006, Niagara Falls, NY, USA.
  11. “Modeling of Binding Sites and Electrostatics in the Ion-Motive Sodium Pump”, J F Fonseca, S Kaya, R F Rakowski and S Guennoun, 6th IEEE Conference on Nanotechnology – IEEENano 2006, 16-20 July, 2006, Cincinnati, OH, USA
  12. “Low-Power Tuneable Analog Circuit Blocks Based on Nanoscale Dual-Gate MOSFETs”, S Kaya, H Hamed and J Starzyk, 6th IEEE Conference on Nanotechnology – IEEE Nano 2006, 16-20 July, 2006, Cincinnati, OH, USA
  13. “Power•Delay Product in COSMOS Logic Circuits”, A Al-Ahmadi and S Kaya11th Int. Workshop of Computational Electronics – IWCE’11, 25-27 May, 2006, Vienna, Austria.
  14. “Electrostatic Modeling of Ion Motive Sodium Pump”, J F Fonseca, S Kaya, and R F Rakowski, 11th Int. Workshop of Computational Electronics – IWCE’11, 25-27 May, 2006, Vienna, Austria.
  15. “Prediction of the location of binding sites in homology models of metal and alkaline-earth ion binding proteins”, Reddy C , J F Fonseca, S Guennoun, S Kaya and R F Rakowski., Swiss Biomedical Research Meeting – USGEB , 23-24 Feb 2006, Geneva, Switzerland.
  16. “Layout and Geometry Tolerances in COSMOS”, A Al-Ahmadi and S KayaInternational Semiconductor Device Research Symposium – ISDRS, 6-9 Dec 2005, Washington DC, USA.
  17. “Study of Dual-Gate SOI MOSFETs as RF Mixers”, Swetha Varadharajan and S Kaya, International Semiconductor Device Research Symposium – ISDRS, 6-9 Dec 2005, Washington DC, USA.
  18. “Homology Study of Na,K ATPases Based on SERCA “, J F Fonseca, S Kaya and R F Rakowski,Mechanisms Of Membrane Transport – A Gordon Research Conference, 5-10 June, 2005, Tilton, New Hampshire, USA.
  19. “Device Scaling in COSMOS Architecture”, A Al-Ahmadi and S Kaya, IEEE 63rd Device Research Conference – DRC’63, 20-22 June, 2005, Santa Barbara, California, USA
  20. “Electro-Chemical Modeling Challenges of Biological Ion Pumps”, R F Rakowski, S Kaya and J F Fonseca, 10th Int. Workshop of Computational Electronics – IWCE’10, 24-26 Oct, 2004, West Lafayette, Indiana, USA.
  21. “Search for Optimum and Scalable COSMOS”, S Kaya and A Al-Ahmadi, 10th Int. Workshop of Computational Electronics – IWCE’10, 24-26 Oct, 2004, West Lafayette, Indiana, USA.
  22. “RF Performance of Strained SiGe pMOSFETs: Linearity and Gain”, W Ma and S Kaya10th Int. Workshop of Computational Electronics – IWCE’10, 24-26 Oct, 2004, West Lafayette, Indiana, USA.
  23. “Simulation of Interface Roughness in DGMOSFETs using Non-Equilibrium Greens Functions”, J Fonseca and S Kaya, IEEE 62nd Device Research Conference – DRC’62, 21-23 June, 2004, South Bend, Indiana, USA
  24. “COSMOS: A New MOS Device Device Paradigm”, S Kaya, Silicon Nanoelectronics Workshop – VLSI Symposia,13-14 Jun 2004, Honolulu, Hawaii,USA.
  25. “Simulation of Interface Roughness in DG-MOSFETs using Non-Equilibrium Green’s Functions”, J Fonseca and S Kaya, IEEE 34th SISC, 04-06 Dec, 2003, Washington, DC.
  26. “Impact of Device Physics on DG and SOI MOSFET Linearity“, W Ma and S.Kaya, Int. Semiconductor Device Research Symposium -ISDRS, 10-12 Dec, 2003, Washington, DC.
  27. J Fonseca and S.Kaya, “Accurate Treatment of Interface Roughness in Nanoscale DGMOSFETs using Non-Equilibrium Green’s Functions”, Int. Semiconductor Device Research Symposium – ISDRS, 10-12 Dec, 2003, Washington, DC
  28. “Design of DG-MOSFETs for High Linearity Performance”, S.Kaya, W Ma and A.Asenov, ,IEEE Int. SOI  Conference, Sep 2003, Newport Beach, California, USA.
  29. “Electro-thermal Analysis of RF Linearity in DG and SOI MOSFETs”, W Ma and  S.Kaya4th OSC Graduate Student Workshop and Conference, 07-08 Aug 2003, Ohio Supercomputer Center, Columbus, Ohio, USA.
  30. “Accurate Treatment of Interface Roughness in Nanoscale MOSFETs using Non-Equilibrium Green’s Functions”, J Fonseca and  S.Kaya4th OSC Graduate Student Workshop and Conference, 07-08 Aug 2003, Ohio Supercomputer Center, Columbus, Ohio, USA.
  31. “Study of RF Linearity in sub-50nm MOSFETs Using Simulations”, W Ma, S.Kaya and A.Asenov, , 9th Int. Workshop of Computational Electronics – IWCE’9, 26-29 May 2003, Frascati, Rome, Italy.
  32. “Breakdown of Universal Mobility due to Atomistic Interface Considerations in nano-MOSFETs”, S Kayaand A Asenov, 4th Motorola Workshop on Computational Materials and Electronics, 14-15 Nov 2002, Tempe, AZ, USA.
  33. “Breakdown of Universal Mobility Curves in sub-100nm MOSFETs”, S Kaya, A Asenov and S. Roy, Silicon Nanoelectronics Workshop – VLSI Symposia,9-10 Jun 2002, Honolulu, HI,USA.
  34. “Implications of Imperfect Interfaces and Edges in Ultra-small MOSFET Characteristics”, A Asenov, S Kaya and A R Brown, 3rd Motorola Workshop on Computational Materials and Electronics, 12-14 Nov 2001, Tempe, AZ, USA.
  35. “On the breakdown of Universal Mobility Curves: A 3D Statistical Simulation Framework”, S Kaya, A Asenov and S. Roy, 8th Int. Workshop of Computational Electronics – IWCE’8, Oct 2001, Urbana-Champaign, IL,USA.
  36. 3D Modelling of Imperfect Interfaces and Edges in MOSFETs, S Kaya, A Brown, S. Roy and A Asenov, Quantum Transport Workshop, 17-22 June 2001, Maratea, Italy.
  37. “Statistical 3D Simulation of Line Edge roughness in Decanano MOSFETs”, A Brown, S Kaya, A Asenov, J H Davies and T. Linton, Silicon Nanoelectronics Workshop – VLSI Symposia,10-11 Jun 2001, Kyoto, Japan.
  38. “Drift Diffusion and Hydrodynamic Simulations of Si/SiGe p-MOSFETs”, Y P Zhao, J R Watling, S Kaya, A Asenov and J R Barker, 5th IUMRS Int. Conference on Advanced Materials, 13-18 Jun 1999, Beijing, China.
  39. “Monte Carlo Investigation of Optimal Device Architectures for SiGe FETs”, S Roy, S Kaya, S Babiker, A Asenov and J R Barker, 6th Int. Workshop of Computational Electronics – IWCE 6, Oct 1998, Osaka, Japan.
  40. “Velocity Overshoot in psuedomorphic Si0.8Ge0.2p-MOSFET’s”, G Ansaripour, G Braithwaite, E H C Parker and T E Whall, S Kaya, Y-P Zhao, J R Watling, A Asenov, J R Barker, 8th European Heterostructure Technology Workshop, 13-15 Sep 1998, Cardiff, UK.
  41. “Strained Si/SiGe Quantum Wells and Wires on Vicinal (118) Si Substrates”, S Kaya, T J Thornton, K Fobelets, P W Green and J M Fernandez, Silicon Nanoelectronics Workshop – VLSI Symposia, 8-9 Jun 1997, Kyoto, Japan.