Refereed Journals

  1. Electrochemically Grown Metallic Nanocomb Structures on Nanoporous Alumina Templates”, S Kaya and E Atar, Appl. Phys Lett. vol.98, p.223105, 2011.
  2. Improved Reconfigurability and Noise Margins in Threshold Logic Gates via Back-Gate Biasing in DG-MOSFETs”, S Kaya, H F A Hamed and D T Ting, J Analog Integr. Circ. & Sig. Process., vol.68, p.101. 2011.
  3. Growth of metallic nanowires on nanoporous alumina templates: Nanocomb Structures“, E Atar, R V Vuppuluri and S Kaya, Proceedings of SPIE, vol. 7768, 77680S, 2010.
  4. Widely tunable low-power high-linearity current-mode integrator built using DG-MOSFETs”, S Kaya, H F A Hamed and A Kulkarni, J Analog Integr. Circ. & Sig. Process., 62(2), 215-222, 2009, DOI 10.1007/s10470-009-9334-6.
  5. Learning Before Erring: A Brief Note on the Influence of Dielectric Materials to Pursue Moore’s Law”, W. A. Young II, S Kaya, and G R Weckman, Int. J of Industrial Engineering – Theory, Applications and Practice, 16(2), 91-98, 2009.
  6. Use of nano-scale double-gate MOSFETs in low-power tunable current mode analog circuits“, H F A Hamed, S Kaya and J Starzyk, J Analog Integr. Circ. & Sig. Process., vol.54, p.211. 2008.
  7. Exploration of Na+,K+-ATPase Ion Permeation Pathways via Molecular Dynamic Simulation and Electrostatic Analysis”, J. E. Fonseca, S. Mishra, S. Kaya and R. F. Rakowski, J Computational Electronics, vol.7, p.20, 2008.
  8. Low-power tunable nanocircuits with DG-MOSFETs for current sensing applications, S Kaya and H F A Hamed, Proceedings of SPIE, vol.6769, 67690D, 2007.
  9. Reconfigurable Threshold Logic Gates with nano-scale DG-MOSFETs”, S Kaya, H F A Hamed, D T Ting and G Creech, Solid-State Electronics, vol. 51, p. 1301, 2007
  10. Temporal and steric analysis of ionic permeation and binding in SERCA via molecular dynamic simulations“, J. E. Fonseca, S. Kaya and R. F. Rakowski, IOP Nanotechnology, vol.18, p.424022, 2007, for an on-line version visit: http://www.iop.org/EJ/abstract/0957-4484/18/42/424022/
  11. Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Dual-Gate MOSFETs“, S Kaya, H F A Hamed and J Starzyk, IEEE Trans Circ. & Sys II, vol. 54, p. 571, 2007.
  12. Temporal Analysis of Valence & Electrostatics in Ion-Motive Sodium Pump“, J E Fonseca, S Kaya, S Guennoun and R F Rakowski, J Computational Electronics, vol.6, p.381, 2007.
  13. Power•Delay Product in COSMOS Logic Circuits“, A Al-Ahmadi and S Kaya, J Computational Electronics, vol.5, p.305, 2006.
  14. Electro-Chemical Modeling Challenges of Biological Ion Pumps“, R F Rakowski, S Kaya and J E Fonseca,  J Computational Electronics, vol.4, p.189, 2005.
  15. Search for Optimum and Scalable COSMOS“, S Kaya and A Al-Ahmadi, J Computational Electronics, vol.4, p.119, 2005.
  16. RF Performance of Strained SiGe pMOSFETs: Linearity and Gain“, W Ma and S Kaya, J Computational Electronics, vol.4, p. 269, 2005.
  17. COSMOS: A New MOS Device Device Paradigm“, S Kaya, IEEE Transactions Nanotechnology, vol. 5, p. 588, 2005.
  18. “Optimization of RF linearity DG-MOSFETs”, S.Kaya and W Ma, IEEE Electron Device Letters, vol. 25, p. 308, 2004.
  19. “Impact of device physics on DG and SOI MOSFET linearity”, W Ma and S.Kaya, Solid-State Electronics, vol. 48, p. 1741, 2004
  20. “Accurate treatment of interface roughness in nanoscale DG MOSFETs using non-equilibrium Green’s functions”, J E Fonseca and S.Kaya, Solid-State Electronics, vol. 48, p. 1843, 2004
  21. “Study of RF Linearity in sub-50nm MOSFETs Using Simulations”, W Ma, S.Kaya and A.Asenov, J Computational Electronics, vol.2, pp.347-352, 2003.
  22. “Statistical Fluctuation of Universal Mobility Curves in sub-100nm MOSFETs due to Random Oxide Interface”, S.Kaya, Physica Status Solidi (b), vol.239, p.110, 2003.
  23. “Simulation of Intrinsic Parameter Fluctuations in Decananometre and Nanometre scale MOSFETs”, A.Asenov, A.R.Brown, J.H.Davies, S.Kaya and G.Slavcheva, IEEE Transaction Electron Devices, vol. 50, p. 1837, 2003.
  24. “Intrinsic Parameter Fluctuations in Decananometre MOSFETs Introduced by Gate Line Edge Roughness”, A Asenov, S Kaya and A R Brown, IEEE Transaction Electron Devices, vol. 50, p. 1254, 2003.
  25. “Breakdown of Universal Mobility Curves in sub-100nm MOSFETs”, S Kaya, A Asenov  and S Roy, IEEE Trans Nanotech., vol.1, p.260, 2002.
  26. “On the Breakdown of Universal Mobility Curves in sub-100nm MOSFETs: A 3D Brownian Simulation Framework”, S Kaya, S Roy and A Asenov, J Computational Electronics, p.375, 2002.
  27. “Implications of Imperfect Interfaces and Edges in Ultra-small MOSFET Characteristics”, A Asenov, S Kaya and A R Brown, Physica Status Solidi (b), vol.233, p.101, 2002.
  28. “Intrinsic Threshold Voltage Fluctuations in Decanano MOSFET’s due to Local Oxide Thickness Variations” A Asenov, S Kaya and J H Davies, IEEE Transaction Electron Devices, vol. 49, p. 112, 2002.
  29. “Quantum Corrections to the ‘Atomistic’ MOSFET simulations”, A Asenov, G Slavcheva, S Kaya and R Balasubramaniam, VLSI Design, vol.13, p. 15, 2001.
  30. “On the Mobility Extraction for HMOSFETs”, U N Straube, A G Evans, G Braithwaite, S Kaya, J Watling and A Asenov, Solid-State Electronics, vol. 45, p. 527, 2001.
  31. “Effective Mobilities in Pseudomorphic Si/SiGe/Si p-channel MOSFETs with thin silicon capping layers” M J Palmer, G Braithwaite, T J Grasby , P J Phillips, M J Prest, E H C Parker, T E Whall C P Parry, A M Waite, A G R Evans, S Roy, J R Watling, S Kaya and A Asenov. Applied Physics Letters, 78(10), p. 1424, 2001.
  32. “Oxide Thickness Variation Induced Threshold Voltage Fluctuations in Decanano MOSFET’s: A 3D Density Gradient Simulation Study”, A Asenov, S Kaya, J H Davies and S Saini. Superlattices  & Microstructures, vol. 28, No. 5/6, p. 507, 2000.
  33. “RF Analysis Methodology for Si and SiGe FETs Based on Transient Monte Carlo Simulation” S Roy, S Kaya, A Asenov and J R Barker, IEICE Transactions in Electronics, vol. E83-C, p. 1224, 2000.
  34. “Indication of Velocity Overshoot in strained Si0.8Ge0.2p-channel MOSFET’s”, S Kaya, Y-P Zhao, J R Watling, A Asenov, J R Barker, G Ansaripour, G Braithwaite, E H C Parker and T E Whall, Semiconductor Science & Technology, 15, p. 573, 2000.
  35. “Drift Diffusion and Hydrodynamic Simulations of Si/SiGe p-MOSFETs”, Y P Zhao, J R Watling, S Kaya, A Asenov and J R Barker Material Science & Engineering B, 72, p.180, 2000.
  36. “MOS gated Si:SiGe quantum wells by anodic oxidation” J C Yeoh, P W Green, T J Thornton, S Kaya, K Fobelets and J M Fernández Semiconductor Science & Technology, 13, p.1442, 1998
  37. “Si/SiGe quantum wells grown on vicinal Si(001) substrates: morphology, dislocation dynamics and transport properties”, P Waltereit, J M Fernandez, S Kaya and T J Thornton, Applied Physics Letters, 72(18), p.2262, 1998.
  38. “Evidence For Inter-Miniband Scattering Due to Electron Heating in Si:SiGe Quantum Wells grown on Tilted Substrates” S Kaya, T J Thornton, K Fobelets, P W Green and J M Fernandez, Physica Status Solidi (b), 204, p.227, 1997.
  39. “Si:SiGe Quantum wells grown on (118) substrates: surface morphology and transport properties”, T J Thornton, J M Fernandez, S Kaya, P W Green and K Fobelets Applied Physics Letters, 70(10), p.1278, 1997.